The manufacture and fabrication of semiconductor devices involve lithography processes transferring a mask pattern into a resist layer that covers a semiconductor wafer and that is sensitive to the exposure illumination. In the semiconductor wafer, structures are formed in a plurality of layers, wherein the structures in the various layers have to be aligned to each other. The dimensions of the patterns and the spaces between the patterns must be provided with sufficient tolerance versus a misalignment of the various layers with reference to each other. Each layer may therefore include alignment marks, wherein the alignment marks of different layers have a predetermined relationship to each other when they are correctly registered.
An example of an alignment mark is a box-in-box mark, wherein an outer box is formed in a first layer and a smaller inner box is formed in a second layer. When the two boxes are concentric, the layers are accurately registered, meaning that the masks and the semiconductor wafer have been perfectly aligned to each other in the respective illumination process step. Any alignment error produces a displacement of the boxes relative to each other. Further, the overlay tolerance has to consider displacement errors of mask structures relative to each other. Typically, alignment marks are used also as registration marks to survey or measure the mask pattern on the mask. If the positions of the registration marks on the mask meet a predetermined specification and their displacement from a respective target position is within an allowable tolerance range, the mask patterns may be provided with a lower tolerance versus an alignment error and the performance of devices emerging from the structures on the semiconductor wafer and/or the yield may be improved.
A need exists for photomasks and methods of fabricating integrated circuits facilitating the manufacturing of integrated circuits with improved device performance and/or improved yield.